Integrated circuits (ICs) typically contain large numbers of elements that are synchronized to a system clock. Different clock distribution methods can be used to distribute the system clock across the chip to these elements. However, as the clock signal propagates through the clock distribution structure, issues such as process, voltage, and temperature (PVT) variations can impact the delay of the clock signal. In order to ensure proper synchronous behavior, the distributed clock signals may need to be aligned to the system clock. Delay locked loops (DLLs) are typically used to align the distributed clock signals to a reference clock that is running at the same frequency or an integer sub-multiple of the system clock frequency.